Francisco Barat, NXP Semiconductors

In this paper we describe the optimizations done to a DSP to retarget it to Software Defined Radio baseband processing. The basic changes are the addition of two modes that operate on subword data: complex data and dual SIMD (single instruction multiple data) data. The first mode modifies the datapath so it can operate on complex data with half the processor width per component. Complex addition is performed by splitting the ALU in two parts of half the original width. Complex multiplication is performed by splitting the full multiplier into four half width multipliers and two half width additions. The hardware needed to modify the datapath behavior is minimal, barely an extra 10%. With these complex arithmetic operations, the processor achieves a performance improvement ranging from 3x to 7x, depending on the kernel (e.g. FFT, FIR, IIR). In the second mode, the processor registers are divided in half, allowing two sub-words to be stored in a processor register. The performance in this mode typically reaches 2x. The programming tools take full benefit of these new data types by extending the C language with complex and SIMD data types. It also maps the standard C operators to the corresponding complex or SIMD instructions. Final results show that the processor has a 4x increase in performance while at the same time reducing the energy consumption by 40%.